Traditionally, any electronic system or apparatus which has an internal phase-locked loop will try first achieving the lock before doing any other calibration. To achieve a lock, the apparatus or system initiates a PLL Calibration engine which will try to find the best solution for the frequency band.
This frequency band information even though readily available which can be loaded to get a faster PLLLOCK is not recommended as the simulation result of the frequency band may not match with real hardware due to the process variations. The PLL typically takes a few milliseconds to achieve the lock.
In case of subsequent system reset, the PLL(s) must undergo re-calibration and achieve the lock after iterating through the frequency bands which will consume the time (the aforementioned few milliseconds).
It would be highly desirable to avoid this PLL lock time of the aforementioned few milliseconds when implementing a subsequent PLL calibration.